Effective Path Selection for Delay Fault Testing of Sequential Circuits

Detecting false timing paths: experiments on PowerPC microprocessors

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

9.2 On Delay-Untestable Paths and Stuck-Fault Redundancy

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Too Much Delay Fault Coverage Is a Bad Thing

ITC '01 Proceedings of the 2001 IEEE International Test Conference

AC Scan Path Selection for Physical Debugging

IEEE Design & Test

Optimal statistical chip disposition

Proceedings of the International Conference on Computer-Aided Design