Proceedings of the 39th annual Design Automation Conference
Effective Path Selection for Delay Fault Testing of Sequential Circuits
Proceedings of the IEEE International Test Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Path-RO: a novel on-chip critical path delay measurement under process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
Optimal test margin computation for at-speed structural test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
A chip disposition criterion is used to decide whether to accept or discard a chip during chip testing. Its quality directly impacts both yield and product quality loss (PQL). The importance becomes even more significant with the increasingly large process variation. For the first time, this paper rigorously formulates the optimal chip disposition problem, and proposes an elegant solution. We show that the optimal chip disposition criterion is different from the existing industry practice. Our solution can find the optimal disposition criterion efficiently with better yield under the same PQL constraint, or lower PQL under the same yield constraint.