Proceedings of the 39th annual Design Automation Conference
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical ordering of correlated timing quantities and its application for path ranking
Proceedings of the 46th Annual Design Automation Conference
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Optimal test margin computation for at-speed structural test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
What is the statistical method for at-speed testing?
ACM SIGDA Newsletter
Testability driven statistical path selection
Proceedings of the 48th Design Automation Conference
Optimal statistical chip disposition
Proceedings of the International Conference on Computer-Aided Design
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Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process space, and the union of such paths must be tested to obtain good process space coverage. This paper proposes a novel branch-and-bound algorithm that elegantly and efficiently solves the hitherto open problem of statistical path tracing. The resulting paths are used for at-speed structural testing. A new Test Quality Metric (TQM) is proposed and paths which maximize this metric are selected. After chip timing has been performed, the path selection procedure is extremely efficient. Path selection for a multi-million gate chip design can be completed in a matter of seconds.