Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Proceedings of the 2009 International Conference on Computer-Aided Design
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Manufacturing testing becomes increasingly difficult in the nanometer manufacturing region because of the impacts of process variation on path delays. It has been frequently observed from manufacturing testing that different chips exhibit different speed limiting paths; and different set of paths may fail to meet the timing specification for different chips.