Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ITC '02 Proceedings of the 2002 IEEE International Test Conference
AC Scan Path Selection for Physical Debugging
IEEE Design & Test
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Bound-based identification of timing-violating paths under variability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Statistical ordering of correlated timing quantities and its application for path ranking
Proceedings of the 46th Annual Design Automation Conference
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Process variation-aware test for resistive bridges
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal test margin computation for at-speed structural test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
What is the statistical method for at-speed testing?
ACM SIGDA Newsletter
Graph partition based path selection for testing of small delay defects
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A full lifecycle performance verification methodology for multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Order statistics for correlated random variables and its application to at-speed testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Meeting the tight performance specifications mandated by the customer is critical for contract manufactured ASICs. To address this, at speed test has been employed to detect subtle delay failures in manufacturing. However, the increasing process spread in advanced nanometer ASICs poses considerable challenges to predicting hardware performance from timing models. Performance verification in the presence of process variation is difficult because the critical path is no longer unique. Different paths become frequency limiting in different process corners. In this paper, we present a novel variation-aware method based on statistical timing to select critical paths for structural test. Node criticalities are computed to determine the probabilities of different circuit nodes being on the critical path across process variation. Moreover, path delays are projected into different process corners using their linear delay function forms. Experimental results for three multimillion gate ASICs demonstrate the effectiveness of our methods.