Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical analysis and optimization in the presence of gate and interconnect delay variations
Proceedings of the 2006 international workshop on System-level interconnect prediction
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Clustering based pruning for statistical criticality computation under process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Bound-based identification of timing-violating paths under variability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Statistical ordering of correlated timing quantities and its application for path ranking
Proceedings of the 46th Annual Design Automation Conference
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
Fast and accurate statistical criticality computation under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 47th Design Automation Conference
Testability driven statistical path selection
Proceedings of the 48th Design Automation Conference
Optimal statistical chip disposition
Proceedings of the International Conference on Computer-Aided Design
Fast statistical timing analysis for circuits with post-silicon tunable clock buffers
Proceedings of the International Conference on Computer-Aided Design
On the computation of criticality in statistical timing analysis
Proceedings of the International Conference on Computer-Aided Design
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult since different paths are frequency-limiting in different parts of the multi-dimensional process space. Therefore, it is desirable to have a new diagnostic metric for robust circuit optimization. This paper presents a novel algorithm to compute the criticality probability of every edge in the timing graph of a design with linear complexity in the circuit size. Using industrial benchmarks, we verify the correctness of our criticality computation via Monte Carlo simulation. We also show that for large industrial designs with 442,000 gates, our algorithm computes all edge criticalities in less than 160 seconds.