Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Hierarchical functional timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A statistical static timing analysis considering correlations between delays
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis of Combinational Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
DAC '83 Proceedings of the 20th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
A New Statistical Approach to Timing Analysis of VLSI Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing
Statistical critical path analysis considering correlations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
Electronics beyond nano-scale CMOS
Proceedings of the 43rd annual Design Automation Conference
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
| Hi-index | 0.00 |
For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable effort on accurate modeling and characterization of circuit delay degradation caused by NBTI at different design levels. The search for techniques and methodologies which can aid in effectively minimizing the NBTI effect on circuit delay is still underway. In this work, we present the usage of node criticality computation to drive NBTI-aware timing analysis and optimization. Circuits that have undergone this optimization flow show strong resistance to NBTI delay degradation. For the first time, this work proposes a node criticality computation algorithm under an NBTI-aware timing analysis and optimization framework. Our work provides answers to the following yet unaddressed questions: (a) what is the definition of node criticality in a circuit under the NBTI effect? (b) how do we identify the critical nodes that, once protected, will be immune to NBTI timing degradation? and (c) what are the NBTI effect attenuation approaches? Experimental results indicate that by protecting the critical nodes found by our proposed methodology, circuit delay degradation can be reduced by up to 50%. Combined with peak temperature reduction, the delay degradation can be be further improved.