Modeling crosstalk noise for deep submicron verification tools
Proceedings of the conference on Design, automation and test in Europe
A Model for Crosstalk Noise Evaluation in Deep Submicron Processes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Hierarchical analysis of process variation for mixed-signal systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Capacitive coupling between interconnects can lead to pattern-dependent delay variation. Statistical process variation results in variation in gate and interconnects delays, and interconnect coupling. These effects become increasingly important in deep submicron circuits. In this work, we describe a statistical timing analyzer for combinational circuits that considers these effects. The tool searches for the input vectors that sensitize the longest paths, and searches for the signal couplings that maximize the delay on these paths, and the sensitizations for these couplings. Under those sensitizations the spatially correlated variation in interconnects, parasitics is analyzed to determine the best and worst-case timing behaviors, assuming gate delay variations are random. We demonstrate timing analysis results on a subset of the ISCAS85 benchmark circuits for which we have synthesized layouts.