ARCHGEN: automated synthesis of analog systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rapid frequency-domain analog fault simulation under parameter tolerances
DAC '97 Proceedings of the 34th annual Design Automation Conference
RF microelectronics
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Statistical Tolerance Analysis for Assured Analog Test Coverage
Journal of Electronic Testing: Theory and Applications
Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Distributed Algorithm for Delay-Constrained Unicast Routing
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Hierarchical tolerance analysis using statistical behavioral models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast true delay estimation during high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AMGIE-A synthesis environment for CMOS analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design Considerations for High Performance RF Cores Based on Process Variation Study
Journal of Electronic Testing: Theory and Applications
Proceedings of the Conference on Design, Automation and Test in Europe
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Increasing process variability necessitates reliable analysis of its effects on circuit performance not only at the top level but also at intermediate levels. Mixed-signal circuits with multiple hierarchical layers, multiple parameters, and complex functional relations are especially susceptible to such variations. In this paper, we present a hierarchical method for process variation analysis. The ability to compute the variance of parameters at each hierarchical layer makes the method particularly suited for helping designers through design iterations. Experimental results indicate that the proposed method achieves high computational efficiency with up to 2% compromise in accuracy even for highly non-linear functional relations.