ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Hierarchical analysis of process variation for mixed-signal systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SRAM read/write margin enhancements using FinFETs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16 Å EOT-70nm transistors (standard process) or 21 -90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1Mbit SRAM instances, based on a highly manufacturable 6T 1.36µm虏 memory cell, have beenprocessed. The cell is detailed and its features, both electrical and morphological, are discussed.