FinFET-based SRAM design

Authors:
Zheng Guo;Sriram Balasubramanian;Radu Zlatanovici;Tsu-Jae King;Borivoje Nikolić
Affiliations:
University of California, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA
Venue:
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Year:
2005

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Abstract

Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty. Up to 2x improvement in SNM can be achieved in 6-T FinFET-based SRAM cells. A 4-T FinFET-based SRAM cell with built-in feedback can achieve sub-100pA per-cell standby current and offer the similar improvements in SNM as the 6-T cell with feedback, making them attractive for low-power, low-voltage applications