Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Current Signatures: Application
Proceedings of the IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Deep Sub-Micron IDDQ Testing: Issues and Solutions
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Transient Current Testing of 0.25 µm CMOS Devices
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Voltage- and ABB-island optimization in high level synthesis
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
SRAM read/write margin enhancements using FinFETs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modelling the impact of high level leakage optimization techniques on the delay of RT-components
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Towards variation-aware system-level power estimation of DRAMs: an empirical approach
Proceedings of the 50th Annual Design Automation Conference
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Barriers to technology scaling, such as leakage and parameter variations, challenge the effectiveness of current-based test techniques. This correlative multi-parameter test approach improves current testing sensitivity, exploiting dependencies of transistor and circuit leakage on operating frequency, temperature, and body bias to discriminate fast but intrinsically leaky ICs from defective ones.