Modelling the impact of high level leakage optimization techniques on the delay of RT-components

Authors:
Marko Hoyer;Domenik Helms;Wolfgang Nebel
Affiliations:
OFFIS Research Institute, Oldenburg, Germany;OFFIS Research Institute, Oldenburg, Germany;University of Oldenburg, Oldenburg, Germany
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

To adress the problem of static power consumption, approaches as ABB and AVS have been proposed to reduce runtime leakage in integrated circuits. Applying these techniques is a trade off between power and delay, which is best decided early in the design flow. Therefore high level power and delay estimation is needed. In our work, we present a fast RT Level delay macro model considering supply and bias voltages and temperature. Errors below 5% combined with only few characterization data enables this approach to be used by high level design tools to support leakage optimization by e.g. ABB and AVS.