RTL power modeling and estimation of sleep transistor based power gating

Authors:
Sven Rosinger;Domenik Helms;Wolfgang Nebel
Affiliations:
OFFIS Research Institute, Oldenburg, Germany;OFFIS Research Institute, Oldenburg, Germany;University of Oldenburg, Oldenburg, Germany
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

Citing 9
Cited 0

Transistor sizing issues and tool for multi-threshold CMOS technology

DAC '97 Proceedings of the 34th annual Design Automation Conference
Dynamic Power Management: Design Techniques and CAD Tools

Dynamic Power Management: Design Techniques and CAD Tools
Power Aware Design Methodologies

Power Aware Design Methodologies
Microarchitectural techniques for power gating of execution units

Proceedings of the 2004 international symposium on Low power electronics and design
Levenberg-Marquardt methods with strong local convergence properties for solving nonlinear equations with convex constraints

Journal of Computational and Applied Mathematics
Benefits and Costs of Power-Gating Technique

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Sleep transistor sizing using timing criticality and temporal currents

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Accurate PTV, state, and ABB aware RTL blackbox modeling of subthreshold, gate, and PN-Junction leakage

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Modelling the impact of high level leakage optimization techniques on the delay of RT-components

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present an accurate RT level estimation methodology describing the power consumption of a component under power gating. By developing separate models for the on- and off-state and the transition cost between them, we can limit errors to below 10% compared to SPICE. The models support several implementation styles of power gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate. We show, how the models can be integrated into a high level power estimation framework supporting design space exploration for several design for leakage methodologies.