Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Efficient techniques for gate leakage estimation
Proceedings of the 2003 international symposium on Low power electronics and design
Characterization and modeling of run-time techniques for leakage power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Experiences of low power design implementation and verification
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic power gating with quality guarantees
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
RTL power modeling and estimation of sleep transistor based power gating
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
The challenges of implementing fine-grained power gating
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Stacking SRAM banks for ultra low power standby mode operation
Proceedings of the 47th Design Automation Conference
Low-power baseband processing for wireless multimedia systems using unequal error protection
WTS'10 Proceedings of the 9th conference on Wireless telecommunications symposium
A Structural Customization Approach for Low Power Embedded Systems Design
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Reliability analysis and optimization of power-gated ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoupling for power gating: sources of power noise and design strategies
Proceedings of the 48th Design Automation Conference
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Hierarchical power management for adaptive tightly-coupled processor arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
RTL power modeling and estimation of sleep transistor based power gating
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Efficient multiple-bit retention register assignment for power gated design: concept and algorithms
Proceedings of the International Conference on Computer-Aided Design
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Flicker: a dynamically adaptive architecture for power limited multicore systems
Proceedings of the 40th Annual International Symposium on Computer Architecture
Agile, efficient virtualization power management with low-latency server power states
Proceedings of the 40th Annual International Symposium on Computer Architecture
Current density aware power switch placement algorithm for power gating designs
Proceedings of the 2014 on International symposium on physical design
| Hi-index | 0.00 |
Power-gating is a technique for saving leakage power by shutting off the idle blocks. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and may make the technique not worth the effort. In this paper, we report on our study of the benefits and costs of the power-gating technique in terms of power, area, and performance. We model and analyze several strongly related parameters such as sleep-transistor size, decap area, and supply voltage level. We also report on our experiments to demonstrate how the gated area, circuit behavior and power mesh granularity affect the power gating technique at the system level. Experimental results show that, by compromising 4% of the total area and 5% of the dynamic power, we can achieve 47% leakage power saving while maintaining the same performance. With technology scaling down, the saving is significant. We conclude that we can benefit from the power-gating technique in future technology nodes.