Guarded evaluation: pushing power management to logic synthesis/design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Dynamic voltage scaling and power management for portable systems
Proceedings of the 38th annual Design Automation Conference
Low-power technology mapping for mixed-swing logic
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
PEAS-III: An ASIP Design Environment
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Low power design using dual threshold voltage
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Application Specific Low Power ALU Design
EUC '08 Proceedings of the 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing - Volume 01
CPU Design: Answers to Frequently Asked Questions
CPU Design: Answers to Frequently Asked Questions
Transistor sizing for low power CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Power consumption is a critical design issue in embedded systems. This paper presents a structural customization approach, targeting two basic design structures for a multiple choice function that is common in an embedded system: tree structure and chain structure. A theoretical comparison between these two structures is performed. We find that the chain structure has a lower area cost and offers more customization opportunities, for improving performance and power efficiency, than the tree structure. We then propose two algorithms to reduce power consumption of the chain design for different performance constraints. A case study on ALU (Arithmetic and Logic Unit) customization has been carried out, Our experiments show that up to 50 percent of ALU power consumption can be saved with our customization approach.