MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Design Challenges of Technology Scaling
IEEE Micro
Design and CAD Challenges in sub-90nm CMOS Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Experimental measurement of a novel power gating structure with intermediate power saving mode
Proceedings of the 2004 international symposium on Low power electronics and design
Experiences of low power design implementation and verification
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Proceedings of the 45th annual Design Automation Conference
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Semicustom design of zigzag power-gated circuits in standard cell elements
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Proceedings of the 7th ACM international conference on Computing frontiers
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wakeup synthesis and its buffered tree construction for power gating circuit designs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A Structural Customization Approach for Low Power Embedded Systems Design
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Low power finite state machine synthesis using power-gating
Integration, the VLSI Journal
ACM Transactions on Architecture and Code Optimization (TACO)
Decoupling for power gating: sources of power noise and design strategies
Proceedings of the 48th Design Automation Conference
Filters that remember: duty cycling analog circuits for long term medical monitoring
Proceedings of the 2nd Conference on Wireless Health
Proceedings of the International Conference on Computer-Aided Design
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia
Proceedings of the International Conference on Computer-Aided Design
Selective instruction set muting for energy-aware adaptive processors
Proceedings of the International Conference on Computer-Aided Design
Stepwise sleep depth control for run-time leakage power saving
Proceedings of the great lakes symposium on VLSI
TAP: token-based adaptive power gating
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A fast and Effective DFT for test and diagnosis of power switches in SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Formal verification of architectural power intent
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. Our simulations and data traces show that multiple sleep mode capability provides an extra 17% reduction in overall leakage as compared to single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit.