Power estimation methods for sequential logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout techniques supporting the use of dual supply voltages for cell-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automated selective multi-threshold design for ultra-low standby applications
Proceedings of the 2002 international symposium on Low power electronics and design
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wakeup synthesis and its buffered tree construction for power gating circuit designs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
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Zigzag power gating (ZPG) can overcome the long wake-up delay of standard power gating, but its requirement for both nMOS and pMOS current switches, in a zigzag pattern, requires complicated power networks, limiting application to custom designs. We propose a design framework for cell-based semicustom design of ZPG circuits, using a new power network architecture that allows the unmodified conventional logic cells to be combined with custom circuitry such as ZPG flip-flops, input forcing circuits, and current switches. The design flow, from register transfer level description to layout, is described and applied to a 32-b microprocessor design using a 1.2-V 65-nm triple-well bulk CMOS process. The use of a sleep vector in ZPG requires additional switching power when entering standby mode and returning to active mode. The switching power should be minimized so that is does not outweigh the leakage saved by employing ZPG scheme. We formulate the selection of a sleep vector as a multiobjective optimization problem, minimizing both the transition energy and the total wirelength of a design. We solve the problem by employing multiobjective genetic-based algorithm. Experimental results show an average saving of 39% in transition energy and 8% in total wirelength for several benchmark circuits in 65-nm technology.