Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Delay modeling and static timing analysis for MTCMOS circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Low-power fanout optimization using MTCMOS and multi-Vt techniques
Proceedings of the 2006 international symposium on Low power electronics and design
Sleep transistor distribution in row-based MTCMOS designs
Proceedings of the 17th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel performance driven power gating based on distributed sleep transistor network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A scalable algorithmic framework for row-based power-gating
Proceedings of the conference on Design, automation and test in Europe
A robust power gating structure and power mode transition strategy for MTCMOS design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semicustom design of zigzag power-gated circuits in standard cell elements
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wakeup synthesis and its buffered tree construction for power gating circuit designs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Design and optimization of power-gated circuits with autonomous data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Low-Power 32bit×32bit multiplier design with pipelined block-wise shutdown
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.