Delay modeling and static timing analysis for MTCMOS circuits

Authors:
Naoaki Ohkubo;Kimiyoshi Usami
Affiliations:
Shibaura Institute of Technology, Munuma-ku, Saitama, Japan;Shibaura Institute of Technology, Munuma-ku, Saitama, Japan
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

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Abstract

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.