Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Circuit-level techniques to control gate leakage for sub-100nm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Low power integrated scan-retention mechanism
Proceedings of the 2002 international symposium on Low power electronics and design
Automated selective multi-threshold design for ultra-low standby applications
Proceedings of the 2002 international symposium on Low power electronics and design
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
An MTCMOS design methodology and its application to mobile computing
Proceedings of the 2003 international symposium on Low power electronics and design
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Reverse-body bias and supply collapse for low effective standby power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
Enhanced leakage reduction Technique by gate replacement
Proceedings of the 42nd annual Design Automation Conference
A novel synthesis approach for active leakage power reduction using dynamic supply gating
Proceedings of the 42nd annual Design Automation Conference
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Delay modeling and static timing analysis for MTCMOS circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Sleep transistor distribution in row-based MTCMOS designs
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Sleep transistor sizing and control for resonant supply noise damping
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Power-gating-aware high-level synthesis
Proceedings of the 13th international symposium on Low power electronics and design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Design and application of multimodal power gating structures
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Semicustom design of zigzag power-gated circuits in standard cell elements
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis and implementation of active mode power gating circuits
Proceedings of the 47th Design Automation Conference
Design and optimization of power-gated circuits with autonomous data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-length biasing for runtime-leakage control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Charge Recycling in Power-Gated CMOS Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TAP: token-based adaptive power gating
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Active-mode leakage reduction with data-retained power gating
Proceedings of the Conference on Design, Automation and Test in Europe
MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging rule-based designs for automatic power domain partitioning
Proceedings of the International Conference on Computer-Aided Design
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Power Gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power Gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.