Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Modeling and analysis of leakage power considering within-die process variations

Proceedings of the 2002 international symposium on Low power electronics and design

Subthreshold leakage modeling and reduction techniques

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Challenges and design choices in nanoscale CMOS

ACM Journal on Emerging Technologies in Computing Systems (JETC)

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization

Integration, the VLSI Journal

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation

Microelectronics Journal

Frequency and yield optimization using power gates in power-constrained designs

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design

Mitigating the impact of variability on chip-multiprocessor power and performance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Optimized self-tuning for circuit aging

Proceedings of the Conference on Design, Automation and Test in Europe

A scalable circuit-architecture co-design to improve memory yield for high-performance processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Runtime leakage minimization through probability-aware optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems