A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

Authors:
Mauro Olivieri;Giuseppe Scotti;Alessandro Trifiletti
Affiliations:
Electronic Engineering Department, University of Rome "La Sapienza," 00184 Rome, Italy;Electronic Engineering Department, University of Rome "La Sapienza," 00184 Rome, Italy;Electronic Engineering Department, University of Rome "La Sapienza," 00184 Rome, Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

Citing 5
Cited 5

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ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Scaling of stack effect and its application for leakage reduction

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads

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An analog on-chip adaptive body bias calibration for reducing mismatches in transistor pairs

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A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A low-voltage low-power threshold voltage monitor for CMOS process sensing

Analog Integrated Circuits and Signal Processing
On-chip process variations compensation using an analog adaptive body bias (A-ABB)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

Microelectronics Journal

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Abstract

This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13-µm CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die.