Scaling of stack effect and its application for leakage reduction

DRG-cache: a data retention gated-ground cache for low power

Proceedings of the 39th annual Design Automation Conference

Dynamic fine-grain leakage reduction using leakage-biased bitlines

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture

Fine-grain CAM-tag cache resizing using miss tags

Proceedings of the 2002 international symposium on Low power electronics and design

Robust SAT-Based Search Algorithm for Leakage Power Reduction

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Subthreshold leakage modeling and reduction techniques

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Implications of technology scaling on leakage reduction techniques

Proceedings of the 40th annual Design Automation Conference

Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Design methodology for fine-grained leakage control in MTCMOS

Proceedings of the 2003 international symposium on Low power electronics and design

New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology

Proceedings of the 2003 international symposium on Low power electronics and design

Elements of low power design for integrated systems

Proceedings of the 2003 international symposium on Low power electronics and design

Active leakage power optimization for FPGAs

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Circuit and microarchitectural techniques for reducing cache leakage power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

LECTOR: a technique for leakage reduction in CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IDDX-based test methods: A survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Nanoscale CMOS circuit leakage power reduction by double-gate device

Proceedings of the 2004 international symposium on Low power electronics and design

Total power optimization through simultaneously multiple-vDD multiple-vTH assignment and device sizing with stack forcing

Proceedings of the 2004 international symposium on Low power electronics and design

Review and future prospects of low-voltage RAM circuits

IBM Journal of Research and Development

Sleep switch dual threshold voltage domino logic with reduced standby leakage current

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

An efficient surface-based low-power buffer insertion algorithm

Proceedings of the 2005 international symposium on Physical design

Scaling trends in adiabatic logic

Proceedings of the 2nd conference on Computing frontiers

Challenges and design choices in nanoscale CMOS

ACM Journal on Emerging Technologies in Computing Systems (JETC)

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Analysis of data dependence of leakage current in CMOS cryptographic hardware

Proceedings of the 17th ACM Great Lakes symposium on VLSI

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Reducing parasitic BJT effects in partially depleted SOI digital logic circuits

Microelectronics Journal

VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies

ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems

Enhanced leakage reduction techniques using intermediate strength power gating

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

UDSM subthreshold leakage model for NMOS transistor stacks

Microelectronics Journal

Techniques for leakage energy reduction in deep submicrometer cache memories

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Sleepy stack leakage reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Journal of Signal Processing Systems

Low-power programmable FPGA routing circuitry

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Standby leakage reduction in nanoscale CMOS VLSI circuits

Proceedings of the International Conference and Workshop on Emerging Trends in Technology

Leakage-delay tradeoff in FinFET logic circuits: a comparative analysis with bulk technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Imperfection-immune VLSI logic circuits using carbon nanotube field effect transistors

Proceedings of the Conference on Design, Automation and Test in Europe

Leakage power analysis attacks: a novel class of attacks to nanometer cryptographic circuits

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Asynchronous computing in sense amplifier-based pass transistor logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A new methodology for power-aware transistor sizing: free power recovery (FPR)

PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

An adaptive technique for reducing leakage and dynamic power in register files and reorder buffers

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit

Proceedings of the great lakes symposium on VLSI

Circuit design of a dual-versioning L1 data cache

Integration, the VLSI Journal

Register file write data gating techniques and break-even analysis model

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells

Microelectronics Journal

Sleep mode analysis and optimization with minimal-sized power gating switch for ultra-low Vdd operation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Mixed FBB/RBB: a novel low-leakage technique for FinFET forced stacks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems