Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Low threshold CMOS circuits with low standby current
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Resource Allocation and Binding Approach for Low Leakage Power
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
LECTOR: a technique for leakage reduction in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Most of the portable systems, such as cellular communication devices, and laptop computers operate from a limited power supply. Devices like cell phones have long idle times and operate in standby mode when not in use. Consequently, the extension of battery-based operation time is a significant design goal which can be made possible by controlling the leakage current flowing through the CMOS gate. This article reviews the off-state leakage mechanisms like weak inversion leakage, gate induced drain leakage and channel punchthrough current. Various circuit level techniques to reduce standby leakage and their design trade-off are discussed. Based on the surveyed techniques, a designer would be able to select the appropriate leakage optimization technique for a standby mode.