ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Leakage Power Analysis and Reduction during Behavioral Synthesis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
LECTOR: a technique for leakage reduction in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Exploiting temporal idleness to reduce leakage power in programmable architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A high-level register optimization technique for minimizing leakage and dynamic power
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Standby leakage reduction in nanoscale CMOS VLSI circuits
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Hardware-based load balancing for massive multicore architectures implementing power gating
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing functional unit power consumption and its variation using leakage sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for power-gating functional units in embedded microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
We propose a leakage power minimization approachbased on Multi-threshold CMOS (MTCMOS) technology.A clique partitioning-based resource allocation and bindingalgorithm is presented, which maximizes the idle periodsof modules in the data-path. Modules with significantidle times are selectively bound to MTCMOS instances. Wedeveloped a parameterizable MTCMOS component library,characterized with respect to sleep transistor width. Usingthis characterization, the leakage power-delay trade-offis analyzed and optimal sleep transistor widths are identified.For three well known HLS benchmarks, we obtainan average leakage power reduction of 22.44%. Themain disadvantage of MTCMOS technology is performancedegradation. We present a performance recovery techniquebased on multi-cycling and introduction of slack. Withthis technique, the performance penalty reduces to as lowas 14.28%. We obtain an average leakage power reductionof 17.46% after performance recovery. The averagearea overhead incurred due to the introduction of MTC-MOSmodules is 10.21%. Results are presented for 0.18µmCMOS technology.