Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Resource Allocation and Binding Approach for Low Leakage Power
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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One of the biggest challenges that programmable devices like FPGAs are facing in ultra deep sub-micron regime is the exponential rise in leakage power consumption. As technology shrinks below 90nm, a new design paradigm has to evolve to tackle the issue of leakage power consumption. In this work we focus on a new design methodology for reducing leakage power by exploiting temporal locality in designs and accordingly group them into. clusters that can be switched on and off. We propose a Power State Controller based method, which controls the switching of the clusters from one state to another. We show our technique using Data Flow Graphs where temporal locality can be effectively explored. Our results show that substantial leakage savings can be achieved if temporal idleness of designs can be exploited effectively.