Post-placement leakage optimization for partially dynamically reconfigurable FPGAs

Authors:
Chi-Feng Li;Ping-Hung Yuh;Chia-Lin Yang;Yao-Wen Chang
Affiliations:
National Taiwan University;National Taiwan University;National Taiwan University;National Taiwan University
Venue:
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Year:
2007

Citing 14
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Abstract

As technology continues to shrink, leakage power becomes animportant issue for modern FPGAs. In this paper, we address the leakage issue of partially dynamical reconfigurable FPGAs. We focus on eliminating leakage waste due to the delay between reconfiguration and task execution. We propose a post-placement leakage-aware scheduling algorithm that refines a placement generated by a performance-driven scheduler such that leakage waste is minimized and performance is not sacrificed. Experimental results on real and synthetic designs demonstrate the effectiveness and efficiency of our algorithm on leakage optimization.