Configuration prefetch for single context reconfigurable coprocessors

Authors:
Scott Hauck
Affiliations:
Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Venue:
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Year:
1998

Citing 6
Cited 57

PRISC: programmable reduced instruction set computers

PRISC: programmable reduced instruction set computers
Sequencing run-time reconfigured hardware with software

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Implementation Approaches for Reconfigurable Logic Applications

FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
The Chimaera reconfigurable functional unit

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A dynamic instruction set computer

FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
SpixTools: Introduction and User's Manual

SpixTools: Introduction and User's Manual

Don't Care discovery for FPGA configuration compression

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Memory interfacing and instruction specification for reconfigurable processors

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The effect of reconfigurable units in superscalar processors

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A HW/SW partitioning algorithm for dynamically reconfigurable architectures

Proceedings of the conference on Design, automation and test in Europe
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Configuration management in multi-context reconfigurable systems for simultaneous performance and power optimizations

ISSS '00 Proceedings of the 13th international symposium on System synthesis
Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A framework for reconfigurable computing: task scheduling and context management

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Reconfigurable computing: a survey of systems and software

ACM Computing Surveys (CSUR)
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

Journal of VLSI Signal Processing Systems
Fast Template Placement for Reconfigurable Computing Systems

IEEE Design & Test
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective

IEEE Transactions on Software Engineering
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors

FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers

FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
The MOLEN rho-mu-Coded Processor

FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Configuration Caching and Swapping

FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
HW/SW codesign techniques for dynamically reconfigurable architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model

Proceedings of the tenth international symposium on Hardware/software codesign
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures

Proceedings of the tenth international symposium on Hardware/software codesign
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration Caching Management Techniques for Reconfigurable Computing

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs

RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures

Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling

ACM Transactions on Embedded Computing Systems (TECS)
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Journal of VLSI Signal Processing Systems
Quick Reconfiguration in Clustered Micro-Sequencer

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

Proceedings of the 42nd annual Design Automation Conference
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Run-time reconfigurable systems for digital signal processing applications: a survey

Journal of VLSI Signal Processing Systems
Subtractive and Divisive Inhibition: Effect of Voltage-Dependent Inhibitory Conductances and Noise

Neural Computation
A parallel configuration model for reducing the run-time reconfiguration overhead

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration

Journal of VLSI Signal Processing Systems
Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices

Proceedings of the conference on Design, automation and test in Europe
Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures

Proceedings of the 44th annual Design Automation Conference
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices

Journal of Systems Architecture: the EUROMICRO Journal
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Design flow instantiation for run-time reconfigurable systems: a case study

EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
The minimization of hardware size in reconfigurable embedded platforms

Proceedings of the 2008 ACM symposium on Applied computing
Dynamic coprocessor management for FPGA-enhanced compute platforms

CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems

ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
T-trees: A tree-based representation for temporal and three-dimensional floorplanning

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Task Scheduling for Context Minimization in Dynamically Reconfigurable Platforms

Journal of Signal Processing Systems
Task scheduling for context minimization in dynamically reconfigurable platforms

EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
A dynamically reconfigurable computing model for video processing applications

Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Dynamic acceleration management for SystemC emulation

ACM SIGBED Review - Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES'09)
Maximum edge matching for reconfigurable computing

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs

Proceedings of the 16th Asia and South Pacific Design Automation Conference
System-level power-performance tradeoffs for reconfigurable computing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting application data-parallelism on dynamically reconfigurable architectures: placement and architectural considerations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance of partial reconfiguration in FPGA systems: A survey and a cost model

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A cost model for partial dynamic reconfiguration

Transactions on High-Performance Embedded Architectures and Compilers IV
An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems

ACM Transactions on Embedded Computing Systems (TECS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the power of reconfigurable systems, it is important to develop hardware and software systems to reduce or eliminate this delay. In this paper we propose one technique for significantly reducing the reconfiguration latency: the prefetching of configurations. By loading a configuration into the reconfigurable logic in advance of when it is needed, we can overlap the reconfiguration with useful computation. We demonstrate the power of this technique, and propose an algorithm for automatically adding prefetch operations into reconfigurable applications. This results in a significant decrease in the reconfiguration overhead for these applications.