A high-level microprogrammed processor
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Don't Care discovery for FPGA configuration compression
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Configuration caching vs data caching for striped FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Configuration compression for FPGA-based embedded systems
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Runlength Compression Techniques for FPGA Configurations
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfiguration in network of embedded systems: Challenges and adaptive tracking case study
Journal of Embedded Computing - Real-Time and Embedded Computing Systems
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This paper presents a Micro-Sequencer based reconfigurable system. We introduce the concept of Quick Reconfiguration and compare it with existing "full reconfiguration" schemes. In a typical scenario, reconfiguring a system from one application to another does not require a "full" reconfiguration. Instead we can exploit similarities among various applications to save on reconfiguration time. We show that a significant speedup is gained by using quick reconfiguration on a set of image processing benchmarks, which takes seconds versus hours in traditional FPGA reconfigurations. We evaluate the flexibility, the performance and the parallelism of this architecture with customized functional units. Furthermore, a method was proposed for customizing clustered datapath to improve the throughput of the system. This method accelerates the system by 13 times on average compared to the case where the same algorithm is running on a modern processor. We also map various applications directly onto FPGAs and measure the silicon area and the power consumption and compare to the case where the applications are implemented on micro-sequencers. On average, micro-sequencer takes 31% more area and consumes 23% more power. However, the reconfiguration time is decreased to less than one second on average while for applications directly mapped onto FPGAs, it is near 3000 seconds.