The data compression book (2nd ed.)
The data compression book (2nd ed.)
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A text-compression-based method for code size minimization in embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Loop Pipelining and Optimization for Run Time Reconfiguration
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Runlength Compression Techniques for FPGA Configurations
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Adaptive Cryptographic Engine for IPSec Architectures
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration compression for the Xilinx XC6200 FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Platform-independent methodology for partial reconfiguration
Proceedings of the 1st conference on Computing frontiers
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
An adaptive cryptographic engine for internet protocol security architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Quick Reconfiguration in Clustered Micro-Sequencer
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Hyperreconfigurable architectures and the partition into hypercontexts problem
Journal of Parallel and Distributed Computing
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A new approach to compress the configuration information of programmable devices
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Design Aspects of Multi-level Reconfigurable Architectures
Journal of Signal Processing Systems
Hardware Decompression Techniques for FPGA-Based Embedded Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A configuration system architecture supporting bit-stream compression for FPGAs
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Computers and Electrical Engineering
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FPGAs are a promising technology for developing high-performance embedded systems. The density and performance of FPGAs have drastically improved over the past few years. Consequently, the size of the configuration bit-streams has also increased considerably. As a result, the cost-effectiveness of FPGA-based embedded systems is significantly affected by the memory required for storing various FPGA configurations. This paper proposes a novel compression technique that reduces the memory required for storing FPGA configurations and results in high decompression efficiency. Decompression efficiency corresponds to the decompression hardware cost as well as the decompression rate. The proposed technique is applicable to any SRAM-based FPGA device since configuration bit-streams are processed as raw data. The required decompression hardware is simple and is independent of the individual semantics of configuration bit-streams or specific features of the on-chip configuration mechanism. Moreover, the time to configure the device is not affected by our compression technique. Using our technique, we demonstrate up to $41 \%$ savings in memory for configuration bit-streams of several real-world applications.