The data compression book (2nd ed.)
The data compression book (2nd ed.)
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Virtual private networks: making the right connection
Virtual private networks: making the right connection
An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
A High-Performance Flexible Architecture for Cryptography
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Runlength Compression Techniques for FPGA Configurations
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration compression for the Xilinx XC6200 FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Configuration compression for FPGA-based embedded systems
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Cost effectiveness of an adaptable computing cluster
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Efficient Software Implementation of AES on 32-Bit Platforms
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
On the Design of a Self-Reconfigurable SoPC Based Cryptographic Engine
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
An Analysis of the Cost Effectiveness of an Adaptable Computing Cluster
Cluster Computing
FPGA based Agile Algorithm-On-Demand Co-Processor
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Proceedings of the 2003 ACM/IEEE conference on Supercomputing
SAFE-OPS: An approach to embedded software security
ACM Transactions on Embedded Computing Systems (TECS)
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Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectures have to be flexible enough to adapt to diverse security parameters. This paper proposes an FPGA-based Adaptive Cryptographic Engine (ACE) for IPSec architectures. By taking advantage of FPGA technology, ACE can adapt to diverse security parameters on-the- fly while providing superior performance compared with software-based approaches.For example, for the case of the Advanced Encryption Standard (AES), our techniques lead to throughput speed-up of 4-20 while the latency time is reduced by a factor of 20-700 compared with software-based approaches. We also develop a compression technique that reduces the memory requirements of ACE without the need for dedicated hardware. Though data compression has been extensively studied before, we are not aware of any prior work that addresses the compression problem of FPGA-based platforms with respect to the implementation cost. Using our technique, we demonstrate up to 40% savings in memory for various configuration bitstreams.