Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Two Methods of Rijndael Implementation in Reconfigurable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
An Implementation of DES and AES, Secure against Some Attacks
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
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WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
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Energy evaluation of software implementations of block ciphers under memory constraints
Proceedings of the conference on Design, automation and test in Europe
An area optimized reconfigurable encryptor for AES-Rijndael
Proceedings of the conference on Design, automation and test in Europe
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ISP'06 Proceedings of the 5th WSEAS International Conference on Information Security and Privacy
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WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
New AES Software Speed Records
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ICISC'02 Proceedings of the 5th international conference on Information security and cryptology
Implementation and benchmarking of hardware accelerators for ciphering in LTE terminals
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Side-channel analysis of cryptographic software via early-terminating multiplications
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation of AES algorithm on ARM
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
Can code polymorphism limit information leakage?
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
Problems of Information Transmission
Fast software implementation of AES-CCM on multiprocessors
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AES software implementations on ARM7TDMI
INDOCRYPT'06 Proceedings of the 7th international conference on Cryptology in India
An instruction set extension for fast and memory-efficient AES implementation
CMS'05 Proceedings of the 9th IFIP TC-6 TC-11 international conference on Communications and Multimedia Security
Accelerating AES using instruction set extensions for elliptic curve cryptography
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Cross-layer analysis of protocol delay in mobile devices receiving BCMCS
Wireless Networks
Secure computing with the MPEG RVC framework
Image Communication
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Rijndael is the winner algorithm of the AES contest; therefore it should become the most used symmetric-key cryptographic algorithm. One important application of this new standard is cryptography on smart cards. In this paper we present an optimisation of the Rijndael algorithm to speed up execution on 32-bits processors with memory constraints, such as those used in smart cards. First a theoretical analysis of the Rijndael algorithm and of the proposed optimisation is discussed, and then simulation results of the optimised algorithm on different processors are presented and compared with other reference implementations, as known from the technical literature.