IEEE Transactions on Computers
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
Proceedings of the 39th annual Design Automation Conference
System design methodologies for a wireless security processing platform
Proceedings of the 39th annual Design Automation Conference
A High-Performance Flexible Architecture for Cryptography
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Software Implementation of AES on 32-Bit Platforms
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Reconfigurable Processor Architectures for Mobile Phones
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
Proceedings of the conference on Design, automation and test in Europe
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
Proceedings of the conference on Design, automation and test in Europe
An instruction set extension for fast and memory-efficient AES implementation
CMS'05 Proceedings of the 9th IFIP TC-6 TC-11 international conference on Communications and Multimedia Security
Application space exploration of a heterogeneous run-time configurable digital signal processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. In this paper, we present the design of AES/Rijndael on a dynamically reconfigurable architecture. We will show a performance improvement of three order of magnitude compared to the reference code and up to 24x speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, we show better energy efficiency with respect to the other programmable solutions, obtaining up to 3 Mbit/sec/mW.