Unlocking the design secrets of a 2.29 Gb/s Rijndael processor

Authors:
Patrick R. Schaumont;Henry Kuo;Ingrid M. Verbauwhede
Affiliations:
UCLA Dept of EE, Los Angeles, CA;UCLA, Los Angeles, CA;UCLA, Los Angeles, CA
Venue:
Proceedings of the 39th annual Design Automation Conference
Year:
2002

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Abstract

This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mw of power consumption. We discuss how the high level reference specification in C is translated into a parallel architecture. Design decisions are motivated from a system level viewpoint. The prototyping setup is discussed.