A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Development cost and size estimation starting from high-level specifications
Proceedings of the ninth international symposium on Hardware/software codesign
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Compiler Design Issues for Embedded Processors
IEEE Design & Test
Fast and Guaranteed C Compilation onto the PACT-XPP" Reconfigurable Computing Platform
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Processor Architectures for Mobile Phones
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
Proceedings of the conference on Design, automation and test in Europe
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A high-end real-time digital film processing reconfigurable platform
EURASIP Journal on Embedded Systems
Nomadik®: AMobile Multimedia Application Processor Platform
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC
IEEE Design & Test
Design and implementation of a field programmable CRC circuit architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single- and multi-core configurable AES architectures for flexible security
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Demonstration of an in-band reconfiguration data distribution and network node reconfiguration
Proceedings of the Conference on Design, Automation and Test in Europe
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of signal processing application domains such as video coding, image processing, telecommunications, and cryptography. Performance of signal processing applications is evaluated from measurements performed on a CMOS 90 nm prototype. In order to characterize the application space of the processor, performance is compared with state-of-the-art devices, taking programmability, computational capabilities, and energy efficiency as the main metrics. The device exploits performance and energy efficiency significantly more than general purpose processors, while still maintaining a user-friendly programming approach that mainly relies on software-oriented languages. The device is able to achieve 1.2 to 15 GOPS with an energy efficiency from 2 to 50 GOPS/W when running the selected applications.