IEEE Transactions on Computers
IEEE Micro
A High-Performance Flexible Architecture for Cryptography
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Reconfigurable Processor Architectures for Mobile Phones
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
An efficient multi-core SIMD implementation for H.264/AVC encoder
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Application space exploration of a heterogeneous run-time configurable digital signal processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Linear feedback shift registers (LFSRs) are common structures in many application fields, including cryptography, digital broadcasting and communication. High-throughput requirements need highly parallel implementations, usually accomplished in state of the art system on chips (SoCs) with application specific coprocessors. Although this approach achieves the required performance, it rapidly shows lack of flexibility when those devices are proposed, as an example, for multi-standard modems or for security applications in which run-time update can provide added value. This paper shows the implementation of parallel LFSR-based applications on an embedded adaptive DSP featuring a Pipelined Configurable Gate Array (PiCoGA). With respect to standard embedded FPGAs, pipelined devices usually provide better performance, e.g. in terms of speed, but they commonly show the undeniable drawback of additional design constraints. As a test-case, we consider the implementation of the 32-bit CRC used in the Ethernet standard that achieves on the target architecture up to ~25Gbit/sec throughput, with a parallel LFSR processing 128 bit at time, which is comparable to the performance offered by some ASIC devices.