Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
Digital transmission theory
A Tutorial on CRC Computations
IEEE Micro
Automatic Generation of Parallel CRC Circuits
IEEE Design & Test
Reunion: Complexity-Effective Multicore Redundancy
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A scalable and high performance software iSCSI implementation
FAST'05 Proceedings of the 4th conference on USENIX Conference on File and Storage Technologies - Volume 4
Proceedings of the conference on Design, automation and test in Europe
WSEAS TRANSACTIONS on COMMUNICATIONS
WSEAS Transactions on Information Science and Applications
Effectiveness data transmission error detection using check sum control for military application
MAMECTIS'08 Proceedings of the 10th WSEAS international conference on Mathematical methods, computational techniques and intelligent systems
A novel parallel parity checksum generator complying with ITU-T J.83 annex B
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
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Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial. A few interesting application areas for hardware parallel encoders are pointed out.