High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
The Designer's Guide to VHDL
A Tutorial on CRC Computations
IEEE Micro
IEEE Micro
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Parallel realization of the ATM cell header CRC
Computer Communications
A novel reconfigurable hardware architecture for IP address lookup
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Microprocessors & Microsystems
Design and implementation of a field programmable CRC circuit architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A parallel CRC circuit simultaneously processes multiple data bits. A generic VHDL description of parallel CRC circuits lets designers synthesize CRC circuits for any generator polynomial or required amount of parallelism.