Rephasing: a transformation technique for the manipulation of timing constraints
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Analysis of operation delay and execution rate constraints for embedded systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Constraint analysis for DSP code generation
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A source-level dynamic analysis methodology and tool for high-level synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Decomposition of timed decision tables and its use in presynthesis optimizations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
High-level scheduling model and control synthesis for a broad range of design applications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Semantics and verification of action diagrams with linear timing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rate derivation and its applications to reactive, real-time embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Resource contrained modulo scheduling with global resource sharing
Proceedings of the 11th international symposium on System synthesis
Synchronization detection for multi-process hierarchical synthesis
Proceedings of the 11th international symposium on System synthesis
Timing-driven HW/SW codesign based on task structuring and process timing simulation
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Time constrained modulo scheduling with global resource sharing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hardware synthesis from C/C++ models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power optimization using divide-and-conquer techniques for minimization of the number of operations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Probabilistic Loop Scheduling for Applications with Uncertain Execution Time
IEEE Transactions on Computers
Localized watermarking: methodology and application to operation scheduling
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Synthesis of low-power selectively-clocked systems from high-level specification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Properties and Algorithms for Unfolding of Probabilistic Data-Flow Graphs
Journal of VLSI Signal Processing Systems
A constraint driven approach to loop pipelining and register binding
Proceedings of the conference on Design, automation and test in Europe
Cross-level hierarchical high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Model composition for scheduling analysis in platform design
Proceedings of the 39th annual Design Automation Conference
Hardware-software cosynthesis for digital systems
Readings in hardware/software co-design
Constraint analysis for DSP code generation
Readings in hardware/software co-design
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Constraint satisfaction for relative location assignment and scheduling
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Automatic Generation of Parallel CRC Circuits
IEEE Design & Test
Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time
ICPP '97 Proceedings of the international Conference on Parallel Processing
Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL
Ada-Europe '99 Proceedings of the 1999 Ada-Europe International Conference on Reliable Software Technologies
Algorithm and architecture-level design space exploration using hierarchical data flows
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Operation Serializability for Embedded Systems
EDTC '96 Proceedings of the 1996 European conference on Design and Test
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A framework for interactive analysis of timing constraints in embedded systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Scalable, Cost-Effective, and Flexible Disk System Using High-Performance Embedded-Processors
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Synthesis of low-power selectively-clocked systems from high-level specification
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Proceedings of the 12th international symposium on System synthesis
Constrained software generation for hardware-software systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Redesigning hardware-software systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
An interactive design environment for C-based high-level synthesis of RTL processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |