Lazy data routing and greedy scheduling for application-specific signal processors
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Efficient retargetable code generation using bottom-up tree pattern matching
Computer Languages
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Optimizing stack frame accesses for processors with restricted addressing modes
Software—Practice & Experience
Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Software scheduling in the co-synthesis of reactive real-time systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Instruction set extraction from programmable structures
EURO-DAC '94 Proceedings of the conference on European design automation
DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Conflict modelling and instruction scheduling in code generation for in-house DSP cores
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Retargetable self-test program generation using constraint logic programming
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Memory bank and register allocation in software synthesis for ASIPs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Algorithms for address assignment in DSP code generation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An ASIP instruction set optimization algorithm with functional module sharing constraint
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Efficient code generation for in-house DSP-cores
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Graph Based Processor Model for Retargetable Code Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Formalization and automatic derivation of code generators.
Formalization and automatic derivation of code generators.
Analysis of emerging core-based design lifecycle
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A cosynthesis algorithm for application specific processors with heterogeneous datapaths
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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This tutorial responds to the rapidly increasing useof cores in general and of processor cores in particular for implementingsystems-on-a-chip. In the first part of this text, we willprovide a brief introduction to various cores. Applications can befound in most segments of the embedded systems market. Theseapplications demand for extreme efficiency, and in particular forefficient processor architectures and for efficient embedded software.In the second part of this text, we will show that current compilersdo not provide the required efficiency and we will give anoverview over new compiler optimization techniques, which aimat making assembly language programming for embedded softwareobsolete. These new techniques take advantage of the specialcharacteristics of embedded software and embedded architectures.Due to efficiency considerations, processor architectures optimizedfor application domains or even for particular applications areof interest. This results in a large number of architectures and instructionsets, leading to the requirement for retargeting compilersto those numerous architectures. In the final section of the tutorial,we will present techniques for retargeting compilers to newarchitectures easily. We will show, how compilers can be generatedfrom descriptions of processors. One of the approaches closesthe gap which so far existed between electronic CAD and compiler generation.