Efficient code generation for in-house DSP-cores

Authors:
M. Strik;J. van Meerbergen;A. Timmer;J. Jess;S. Note
Affiliations:
Philips Research Laboratories, WAY 4.47, Prof. Holstlaan 4, 5656 AA, Eindhoven, The Netherlands;Philips Research Laboratories, WAY 4.47, Prof. Holstlaan 4, 5656 AA, Eindhoven, The Netherlands;Eindhoven University of Technology;Eindhoven University of Technology;Philips ITCL, Leuven, Belgium
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

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Abstract

A balance between efficiency and flexibility is obtained by developing a relative large number of in-house DSP-cores each for a relatively small application area. These cores are programmed using existing ASIC synthesis tools which are modified for this purpose. The key problem is to model conflicts arising from the instruction set. A class of instruction sets is defined for which conflicts can be modelled statically before scheduling. The approach is illustrated with a real life example.