Software scheduling in the co-synthesis of reactive real-time systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Data routing: a paradigm for efficient data-path synthesis and code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Code generation for a DSP processor
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
CodeSyn: a retargetable code synthesis system (abstract)
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Execution interval analysis under resource constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Tree-based mapping of algorithms to predefined structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Exact scheduling strategies based on bipartite graph matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Efficient code generation for in-house DSP-cores
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Concurrent analysis techniques for data path timing optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Instruction selection for embedded DSPs with complex instructions
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Constraint analysis for DSP code generation
ISSS '97 Proceedings of the 10th international symposium on System synthesis
An efficient model for DSP code generation: performance, code size, estimated energy
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Exploiting conditional instructions in code generation for embedded VLIW processors
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Constraint analysis for code generation: basic techniques and applications in FACTS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A constraint driven approach to loop pipelining and register binding
Proceedings of the conference on Design, automation and test in Europe
C Compiler Design for an Industrial Network Processor
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Static resource models of instruction sets
Proceedings of the 14th international symposium on Systems synthesis
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
An empirical evaluation of high level transformations for embedded processors
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Constraint analysis for DSP code generation
Readings in hardware/software co-design
Constraint satisfaction for relative location assignment and scheduling
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Array recovery and high-level transformations for DSP applications
ACM Transactions on Embedded Computing Systems (TECS)
Static resource models for code-size efficient embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Instruction-Set Modeling for ASIP Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
The use of a virtual instruction set for the software synthesis of Hw/Sw embedded systems
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Proceedings of the 12th international symposium on System synthesis
A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Fast source-level data assignment to dual memory banks
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Register files constraint satisfaction during scheduling of DSP code
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Adaptive Source-Level Data Assignment to Dual Memory Banks
ACM Transactions on Embedded Computing Systems (TECS)
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