Constraint analysis for DSP code generation

Authors:
Bart Mesman;Marino T. J. Strik;Adwin H. Timmer;Jef L. van Meerbergen;Jochen A. G. Jess
Affiliations:
Philips Research Laboratories, WAY4, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands and Section ICS, Department of Electrical Engineering, Eindhoven University of Technology, The Netherland ...;Philips Research Laboratories, WAY4, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;Philips Research Laboratories, WAY4, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;Philips Research Laboratories, WAY4, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;Section ICS, Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands
Venue:
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Year:
1997

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Abstract

Code generation methods for DSP applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms, and resource constraints imposed by a hardware architecture. In this paper, we present a method to analyze resource- and timing constraints in a single model. The analysis identifies sequencing constraints between operations additional to the precedence constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing and resource constraints. The presented approach results in an efficient method of obtaining high quality instruction schedules.