Estimating architectural resources and performance for high-level synthesis applications
DAC '93 Proceedings of the 30th international Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Exploiting regularity for low-power design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A solution methodology for exact design space exploration in a three-dimensional design space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Execution interval analysis under resource constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Constraint analysis for DSP code generation
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A constraint driven approach to loop pipelining and register binding
Proceedings of the conference on Design, automation and test in Europe
Layout-driven high level synthesis for FPGA based architectures
Proceedings of the conference on Design, automation and test in Europe
Exact scheduling strategies based on bipartite graph matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Constraint analysis for code generation: basic techniques and applications in FACTS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solving difficult SAT instances in the presence of symmetry
Proceedings of the 39th annual Design Automation Conference
Symmetry breaking for multi-criteria mapping and scheduling on multicores
FORMATS'13 Proceedings of the 11th international conference on Formal Modeling and Analysis of Timed Systems
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