MPEG: a video compression standard for multimedia applications
Communications of the ACM - Special issue on digital multimedia systems
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Clock optimization for high-performance pipelined design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A grid-based approach for connectivity binding with geometric costs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Execution interval analysis under resource constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Area and Timing Estimation for Lookup Table Based FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
RTL Synthesis with Physical and Controller Information
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Incorporating performance and testability constraints during binding in high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Identification and exploitation of symmetries in DSP algorithms
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we address the problem of layout-driven scheduling-binding as these steps have a direct relevance on the final performance of the design. The importance of effective and efficient accounting of layout effects is well-established in High-Level Synthesis (HLS),since it allows more efficient exploration of the design space and the generation of solutions with predictable metrics. This feature is highly desirable in order to avoid unnecessary iterations through the design process. By producing not only an RTL netlist but also an approximate physical topology of implementation at the chip level, we ensure that the solution will perform at the predicted metric once implemented, thus avoiding unnecessary delays in the design process.