The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The DT-model: high-level synthesis using data transfers
DAC '98 Proceedings of the 35th annual Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Integrating floorplanning in data-transfer based high-level synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fine grain incremental rescheduling via architectural retiming
Proceedings of the 11th international symposium on System synthesis
Behavioral network graph: unifying the domains of high-level and logic synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Layout-driven high level synthesis for FPGA based architectures
Proceedings of the conference on Design, automation and test in Europe
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
Matisse: An Architectural Design Tool for Commodity ICs
IEEE Design & Test
Optimal slicing of plane point placements
EURO-DAC '90 Proceedings of the conference on European design automation
Hierarchical power supply noise evaluation for early power grid design prediction
Proceedings of the 2001 international workshop on System-level interconnect prediction
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips
Proceedings of the 42nd annual Design Automation Conference
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Layout driven data communication optimization for high level synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Automated design of digital microfluidic lab-on-chip under pin-count constraints
Proceedings of the 2008 international symposium on Physical design
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new methodology of integrating high level synthesis and floorplan for soc design
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A metric for layout-friendly microarchitecture optimization in high-level synthesis
Proceedings of the 49th Annual Design Automation Conference
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Our methodology unifies behavioral synthesis and physical design, allowing scheduling, allocation, binding, and placement to occur simultaneously. This is accomplished via set of defined transformation from both domains acting as forces in a single behavioral/physical system. Experiments show results with 50% less area and 10% lower critical path delay than the best results from a commercial behavioral synthesis tool. Our behavioral level area, delay, and individual component location estimates closely match results produced by physical design tools given only pin locations as a starting point.