3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A grid-based approach for connectivity binding with geometric costs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
C-based behavioral synthesis and verification analysis on industrial design examples
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
A data-centric approach to high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
C-based SoC design flow and EDA tools: an ASIC and system vendor perspective
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As silicon CMOS technology is scaled into the nanometer regime, a whole system can be integrated into one chip. At the same time, the computer-aided design technology is challenged by two major features: the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology. In this paper, a new methodology of integrating High Level Synthesis and Floorplan together is presented. The whole design flow is divided into two phases: a fast searching space scan procedure and a detailed solution optimize procedure. The searching space of integrating HLS and Floorplan is first “smoothed” by a “Behavior Information based Cluster Algorithm”, and then a fast scan of this smoothed searching space is proceeded. The result of the first phrase will be used as the start point of the detailed optimize procedure. The experimental result show that the methodology is efficient.