3D scheduling: high-level synthesis with floorplanning

Combined topological and functionality based delay estimation using a layout-driven approach for high level applications

EURO-DAC '92 Proceedings of the conference on European design automation

A layout estimation algorithm for RTL datapaths

DAC '93 Proceedings of the 30th international Design Automation Conference

An approach for redesigning in data path synthesis

DAC '93 Proceedings of the 30th international Design Automation Conference

Simultaneous functional-unit binding and floorplanning

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

APPlaUSE: A&barbelow;rea and p&barbelow;erformance optimization in a u&barbelow;nified placement and s&barbelow;ynthesis e&barbelow;nvironment

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

False path exclusion in delay analysis of RTL-based datapath-controller designs

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Timing estimation for behavioral descriptions

ISSS '94 Proceedings of the 7th international symposium on High-level synthesis

A grid-based approach for connectivity binding with geometric costs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Layout-driven RTL binding techniques for high-level synthesis using accurate estimators

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Integrating floorplanning in data-transfer based high-level synthesis

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Soft scheduling in high level synthesis

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

A flexible datapath allocation method for architectural synthesis

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Layout-driven high level synthesis for FPGA based architectures

Proceedings of the conference on Design, automation and test in Europe

False path exclusion in delay analysis of RTL structures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Behavior-to-placed RTL synthesis with performance-driven placement

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Interconnect-aware high-level synthesis for low power

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Layout-driven resource sharing in high-level synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Incremental exploration of the combined physical and behavioral design space

Proceedings of the 42nd annual Design Automation Conference

Resource Sharing Combined with Layout Effects in High-Level Synthesis

Journal of VLSI Signal Processing Systems

Compatibility path based binding algorithm for interconnect reduction in high level synthesis

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

An integrated approach to thermal management in high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A global interconnect reduction technique during high level synthesis

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Optimal and heuristic algorithms for solving the binding problem

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A new methodology of integrating high level synthesis and floorplan for soc design

ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems

Towards layout-friendly high-level synthesis

Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design

A metric for layout-friendly microarchitecture optimization in high-level synthesis

Proceedings of the 49th Annual Design Automation Conference