Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

Authors:
A. Stammermann;D. Helms;M. Schulte;A. Schulz;W. Nebel
Affiliations:
OFFIS Research Institute, Germany;OFFIS Research Institute, Germany;OFFIS Research Institute, Germany;Univ. of Oldenburg, Germany;Univ. of Oldenburg, Germany
Venue:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Year:
2003

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Abstract

This work is a contribution to high level synthesis for lowpower systems.While device feature size decreases, interconnectpower becomes a dominating factor.Thus it is importantthat accurate physical information is used during high-level synthesis.We propose a new power optimisation algorithm for RT-levelnetlists.The optimisation performs simultaneously slicing-treestructure-based floorplanning and functional unit binding andallocation.Since floorplanning, binding and allocation can use theinformation generated by the other step, the algorithm can greatlyoptimise the interconnect power.Compared to interconnect unawarepower optimised circuits, it shows that interconnect powercan be reduced by an average of 41.2%, while reducing overallpower by 24.1% on an average.The functional unit power remainsnearly unchanged.These optimisations are not achieved atthe expense of area.